We are seeking a passionate Digital Functional Verification Engineer to play a pivotal role in complex projects : embracing requirements, actively shaping and refining the verification plan, establishing dynamic verification metrics in digital and mixed signal environments, crafting innovative test cases, and ensuring compliance through insightful reporting. This role entails inspiring coordination of verification activities for impactful projects.In your new role you will :
- Contribute to verification in complex projects : understanding requirements, actively support the definition & review of the verification plan, setting up verification metrics in digital & mixed signal environments, developing test cases and ensuring reports compliance. Responsibilities involve coordination of verification activities for given projects.
- Apply methodologies ( Universal Verification Methodology (UVM / UVM-AMS) and execute tests in these environments on RTL, gate-level and mixed-signal designs
- Create reusable verification components and environments
- Closely cooperate with analogue and digital designers as well as concept and verification engineers
- Identify deficiencies in verification methodology and simulation performance, and implement improvements
- Identify and address synergies between Pre-Silicon Verification methodology and Post-Silicon Validation
- This role is not just about verification; it’s about inspiring and mentoring junior verification engineers while providing invaluable technical support and guidance to development teams and business partners
In addition, you will :
Create new and improve existing verification environmentsContribute to create a smooth x-domain verification & validation methodologyActively participate in Infineon verification communitiesProvide technical guidance / assistance when needed in the projects related to interaction topicYou are best equipped for this task if you have :
A degree in Electronics Engineering or similar field of studies with specific knowledge in semiconductor developmentAt least 5 years of pre-silicon verification experience using UVM methodologyDemonstrates technical proficiency with state-of-the-art verification methodologies and tool flows.Act as a technical lead through exploring new environment and identifying potential enhancement areas through new methodologyGood knowledge of VHDL, Verilog, C, C++, SystemVerilogSelf-motivated, flexible, good communication with interpersonal skills and is a good team player who can work well with both internal and external partnersCandidate has proven ability to achieve results in a very dynamic, multi-site environment and be able to coordinate with priorities and self-initiativesDemonstrated innovation driveAbility to improve efficiency through scripting and automationStrong stakeholders management across multiple groups & sitesFluent English communication is mandatoryIt is an advantage if you have :Advantage : Knowledge of analogue & mixed-signal IC verification methodologies and tools ( XA / VCS, AMS-Designer, …)Experience with requirements management methodologiesExperience with automotive standards (ISO26262)Experience as a technical lead and / or mentorBenefits
Wide range of training offers & planning of career developmentInternational assignmentsDifferent career paths : Project Management, Technical Ladder, Management & Individual ContributorStaggered working hours for normal shift employeesHome office options, certain conditions apply.Part-time work possible (applicable for normal shift employees)On-site day-care centerMedical coverageOn-site social counselling and works doctorHealth promotion programsOn-site canteenPrivate insurance offersPaid sick leave according to law, personal accident & work injury insurance, long term illness leaveRetirement benefits, re-employment opportunities, employment assistance paymentPerformance bonusProvision of long haul transport for shift and shuttle services for office to defray transport costs