Physical Design Engineer for Power Management ASICs

Company :

Qualcomm Global Trading Pte. Ltd.

Job Area :

Engineering Group, Engineering Group >

ASICS Engineering

General Summary : Job Description

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in.

Physical Design Engineer for Mixed-Signals IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions. IPs include telemetry ADCs, 100W+ charging (Quick Charge 5.0), 5G power (mmW, envelope tracking, high performance low noise oscillators etc…) and high efficiency power management (DC-DC charge pumps, bucks and linear regulators).

• Successful applicants will be responsible for participating in, or leading, the physical design of state-of-the-art Mixed-Signals ASICs in advanced digital deep sub-micron CMOS processes for multi-function mobile platforms.
• Responsibilities will include all, or some, of the following :
• Own and execute block-level and full-chip physical design from RTL to GDSII.
• Perform floor-planning, placement, clock tree synthesis (CTS), routing, and physical verification (LVS / DRC / ERC).
• Collaborate with RTL, analog, DFT, and verification teams to ensure seamless integration and design closure.
• Drive timing closure using static timing analysis (STA) and resolve signal integrity and EM / IR issues.
• Participate in design reviews and contribute to continuous improvement of PD flows and methodologies.

Preferred Qualifications

Minimum Qualifications

Minimum Qualifications :

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If you would like more information about this role, please contact Qualcomm Careers .

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