Talent.com
This job offer is not available in your country.
Design Verification Engineer

Design Verification Engineer

USTSingapore, Pedra Branca, Singapore
28 days ago
Job description

Get AI-powered advice on this job and more exclusive features.

Talent Acquisition @ UST | Talent Sourcing, Recruitment Strategies

Job Responsibilities :

  • Apply UVM (Universal Verification Methodology), SystemVerilog, Verilog, and SVA (SystemVerilog Assertions) languages in verification tasks
  • Develop and implement state-of-the-art verification methodologies, including UVM, C / C++, co-simulation, system emulation, and mixed-mode simulation / emulation
  • Contribute to projects requiring advanced verification tools such as Palladium Z1, HAPS, and Zebu platforms
  • Collaborate effectively within a team, ensuring high-quality deliverables

Job Requirements :

  • Possesses a Masters or Bachelors degree in Electrical Engineering or Computer Engineering
  • At least 3 years of relevant experience
  • Proficient in UVM, SystemVerilog, Verilog, and SVA languages
  • Strong knowledge in protocols such as SPI, UART, and I2C
  • Possesses knowledge of firmware development and in depth understanding of firmware development processes
  • Excellent team player with strong communication skills.
  • Highly driven and detail-oriented.
  • Has experience working with advanced verification platforms like Palladium Z1, HAPS, or Zebu

    • Seniority level

    Seniority level

    Mid-Senior level

    Employment type

    Employment type

    Full-time

    Job function

    Industries

    Semiconductor Manufacturing

    Referrals increase your chances of interviewing at UST by 2x

    Sign in to set job alerts for “Design Verification Engineer” roles.

    Validation Engineer Trainee - Train and Place Program

    Kallang, Central Singapore Community Development Council, Singapore 4 days ago

    Senior / Staff Engineer, Technical Manager (Design Verification)

    Staff Analog Mixed-Signal Verification Engineer - RF / TIA

    Staff Analog Mixed-Signal Verification Engineer - RF / TIA

    High Energy Efficiency Chip Verification Engineer Intern

    Memory modeling Engineer (Memory Design Automation)

    High Energy Efficiency Chip Verification Engineer

    Senior Staff Analog Mixed-Signal Verification Engineer - RF / TIA / Driver

    Product Engineer - NAND Silicon Design Validation (SDV)

    Senior Staff Analog Mixed-Signal Verification Engineer - RF / TIA / Driver

    Application Specific Integrated Circuit Design Engineer

    Executive / Senior Engineer, Regulations and Process Transformation Department

    High Energy Efficiency Chip Design Engineer Intern

    SSD Verification & Characterization and NAND System Failure Analysis Engineer

    We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

    J-18808-Ljbffr

    Create a job alert for this search

    Design Engineer • Singapore, Pedra Branca, Singapore