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IC Design Engineer (Verilog, EDA, up to $10,000) - D01 Cecil, Marina, People’s Park, Raffles Place, SG

IC Design Engineer (Verilog, EDA, up to $10,000) - D01 Cecil, Marina, People’s Park, Raffles Place, SG

RECRUIT EXPERT PTE. LTD.D01 Cecil, Marina, People’s Park, Raffles Place, SG
6 days ago
Job description

Roles & Responsibilities

  • Implement IC design development of products, Logic Synthesis and Static Timing Analysis
  • Manage DFT related activities - Scan Insertion, ATPG, Pattern Validation
  • Assist in debug & correct any functional issues found in taped-out devices

Requirements :

  • Degree in Electrical / Electronics Engineering or equivalent
  • At least 5 years of digital IC design experience using EDA tools (Cadence, Synopsys)
  • Proficiency in Verilog HDL and VHDL RTL design, Logic Synthesis, DFT, ATPG, Timing Closure

    • If you are keen to apply for the position, kindly email your detailed resume in MS Word to hr@recruit-expert.com

    Please note that only shortlisted candidates will be notified.

    For more job opportunities, please visit our website at www.recruit-expert.com

    EA Licence : 19C9701

    Registration : R1326740

    Tell employers what skills you have

    VHDL

    Static Timing Analysis

    Timing Closure

    EDA

    MS Word

    RTL Design

    Cadence

    DFT

    IC

    Atpg

    Verilog

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    Design Engineer • D01 Cecil, Marina, People’s Park, Raffles Place, SG