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Senior Scientist (SiC MOS Gate Interface & Stack Process), (SiC), IME

A •STARSingapur

30+ days ago

Job description

ROLE :

STAR-IME is spearheading the establishment of the Silicon Carbide (SiC) R&D program. This initiative aims to advance 200mm Silicon Carbide technologies across various areas including epitaxy, device design, process integration & fabrication, and power module packaging. The primary goal is to catalyze disruptive innovations in power device research, focusing particularly on >

1.2KV power MOSFETs. These innovations are targeted towards enhancing automotive technologies, vehicle electrification, safety measures, sustainable energy grids, data centers, and industrial & aerospace automation. One of the critical challenges in SiC MOSFETs fabrication lies in gate stack formation and interface characterization. For this purpose, a skillful lead with hands-on experience, proactive motivation, quick learning abilities, and strong interpersonal skills is being sought to contribute to gate stack design and interface characterization. This candidate will be also groomed to lead a front-end team of ~5 headcounts for wide-bandgap integration in the next 3 years.

RESPONSIBILITIES :

Candidate will perform detailed design of experiments for gate stacks optimizations; aimed to develop highly reliable SiC MOS gate module technology.

To conduct hands-on work for MOSCAP process & interface characterizations, including MOS CV & variable frequency CV analysis, DLTS characterization, and more.

Responsible for analyzing electrical test data, benchmarking with publicly available results, and apply established physics-based theories of interface trap behavior in 4H-SiC

Collaborate with the project members to ensure gate oxide goals meet performances, quality, and reliability standards aligned to customer expectations

Ensure that design of experiments stays on schedule and mitigate overall risks

Engage with diverse teams, including process integration, characterization, and advanced process modules, to analyze & debug device / process-related challenges

Working closely with internal and external customers to understand their demands and mitigate their issues

REQUIREMENTS :

PhD Degree in Electrical Engineering or related field

Up to 3 years of relevant industry experience

MOSCAP layout design with good understanding of the gate interface, gate dielectric materials at the atomic level and ALD of high-k dielectric materials will be required

Solid understanding of MOSFET and HEMT device physics, preferably with SiC and GaN materials