Senior / Staff Engineer, Technical Manager (Design Verification)

Job Descriptiono Develop and review test plans

o Develop verification environment / testbench in Module / IP / SOC level

o Develop verification IP and reference model

o Implement test with randomization based coverage driven verification methodology

o Implement functional and functional / code coverage closure

o Hands-on code / debug with UVM, SystemVerilog, Verilog and SystemC :

• Low Power verification
• Formal verificationRequirement
• Bachelor's / Master's Degree in EEE / Computer / IC design
• 4-10 years verification experiences
• IC / ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU
• Strong experience and debugging ability on SystemVerilog / UVM
• Skilled in Synopsys / Cadence / Mentor Simulator and debugging flow
• Experience on Low Power and formal verification is a plus
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell
• Quick to learn new technology