RTL Design Engineer (ASIC / SOC / Verilog / System Verilog) - D22 Jurong, Jurong Island, Tuas, SG

Roles & Responsibilities

Responsibilities :

• Lead RTL design, simulation, and verification for company ASIC / SoC products, ensuring robustness.
• Integrate and validate IP blocks for seamless system functionality.
• Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.
• Collaborate with backend team in RTL coding, implementation, and synthesis for successful tapeout.
• Create and maintain reusable IPs for AI / in-memory computing.
• Support Post-Si testing to ensure product functionality and quality.
• Mentor junior engineers to facilitate their professional growth.
• Contribute to design reviews for improved product performance and reliability.
• Stay current on RTL design methodologies for efficiency and quality.
• Collaborate with cross-functional teams for successful product development.

Requirements :

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HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact win@hkmsvs.com for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and / or last employment

2) Last drawn and / or current salary

3) Expected salary

4) Date of availability and / or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Tell employers what skills you have

Designer

Microsoft PowerPoint

Adobe Creative Suite

Reliability

RTL Design

IP

FPGA

Adobe Illustrator

VCS

SystemVerilog

Adobe After Effects

Product Development

Verilog

Electrical Engineering

Adobe Photoshop

C++