SOC Verification Engineer

Roles & Responsibilities

* Fresh graduates are welcome to apply

Job Responsibilities:-

• Pre-silicon RTL verification of block, IP and top level SOC using best-in-class verification methodology
• Develop reusable testbench and verification environment in SV UVM
• Create verification plan from specification and in coordination with architects
• Create directed and constrained random test case to verify functional correctness and performance of the design
• Own and debug failures in simulation to root-cause problems
• Co-work with Architecture/ Design/Validation/SW teams. Own cross functional debug and drive issues to closure

Job Requirements:-

• Bachelor Degree in Electronics Engineering with 6 years or Master's with 3 years of experience
• Expert in Front End Verification using best-in-class verification methodology SV-UVM
• Should have developed SV -UVM test benches for multiple projects
• Participated in complete verification cycle including coverage closure and Gate Sims
• Expertise in defining test plans for Block, IP, Sub-System , SoC verification
• Solid verification skills in problem solving, constrained random testing and debugging
• Expertise with simulation, regressions and coverage tracking tools such as NCSIM/Xcelium/VCS/Verdi etc
• Programming experience in C/C++/assembly/SVA. Experience in Perl or Python is a plus
• Experience of working with PCIe, AXI, AHB, SERDES systems, communication peripherals(UART, I2C, SPI), power management
• Experience in WiFi/DOCSIS/DSP/DDR is a plus
• Setup Automated regressions environment and in general automate repetitive verification tasks to enhance productivity
• Strong team player and communicator

Location: Next to Bendemeer MRT

Interested candidatesmay submit detailed CV with the following info:-

• Current salary, including AWS or Variable Bonus
• Expected salary
• Availability

Tell employers what skills you have

Perl
PCIe
SERDES
Root Cause Analysis
Problem Solving
C/C++
IP
Python
DSP
Verification and Validation (software)
Test Environments
UART
Test bench setup
Architectural Plans
I2C