IC Design Engineer (Verilog, EDA, up to $10,000) - D01 Cecil, Marina, People’s Park, Raffles Place, SG

Roles & Responsibilities

• Implement IC design development of products, Logic Synthesis and Static Timing Analysis
• Manage DFT related activities - Scan Insertion, ATPG, Pattern Validation
• Assist in debug & correct any functional issues found in taped-out devices

Requirements :

If you are keen to apply for the position, kindly email your detailed resume in MS Word to hr@recruit-expert.com

Please note that only shortlisted candidates will be notified.

For more job opportunities, please visit our website at www.recruit-expert.com

EA Licence : 19C9701

Registration : R1326740

Tell employers what skills you have

VHDL

Static Timing Analysis

Timing Closure

EDA

MS Word

RTL Design

Cadence

DFT

IC

Atpg

Verilog