ISP RTL Design Engineer - D22 Jurong, Jurong Island, Tuas, SG

Roles & Responsibilities

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and / or SystemC (High Level Synthesis)
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

Tell employers what skills you have

Image Processing

RTL Coding

Electrical

Digital Design

RTL Design

CMOS

C Programming

SystemVerilog

Debugging

Verilog

SystemC

Manufacturing

Electrical Engineering

Algorithms

C++