Roles & Responsibilities
West area - Pick up at Jurong East & Drop off at Boon Lay
8.30AM to 6.00PM (Mon - Fri)
Responsibilities
- Responsible for silicon photonics chip design, simulation, and layout implementation
- Based on the SOI / CMOS process platform, complete link-level modeling, layout design, and verification of key devices such as silicon-based modulators and detectors
- Responsible for chip-level signal integrity (simulation and test verification), addressing issues related to high-speed parasitics, crosstalk, and packaging losses
Requirements
Bachelor in Physics, minoring in Optical Engineering or preferably, Bachelor / Masters in Optical EngineeringOver 5 years of experience in silicon photonics chip or high-speed optical module optical design, with prior experience in full-scale production and mass production preferredFamiliarity with silicon photonics processes (SOI, SiN, CMOS-compatible processes) and common failure mechanisms, with a strong understanding of DFM / DFT principles;Prior successful experience in designing optical modules at 400G / 800G or higher speeds, or coherent communication silicon photonics chips, is preferredEntry level candidates in relevant field are welcomed to applyJessica Nguyen Huynh Thanh Truc
CEI Reg. No. R23113787
EA License No. 99C4599
We regret that only shortlisted candidates will be notified.
Tell employers what skills you have
Signal Integrity
Silicon Photonics
Modeling
Physics
Reliability
Photonics
Packaging
Team Player
Layout
Silicon