Physical Design Engineer - Singapore

Responsibilities

Team Introduction

The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power / IR / EM). The team also oversees tape‑out, mass production, packaging, testing, and board‑level verification. They collaborate closely with front‑end chip teams across business units to drive R&D progress and mass production deployment for chip.

1. Responsible for the block / chip level physical design, from Netlist to GDSII, including Floorplan, Auto Place and Routing, PPA push and signoff work such as Physical Verification / STA / IREM etc.

2. As the foundry contact window, participate in new process introduction, chip tapeout, mass production, packaging and testing, quality control, and other tasks.

3. Participate in project plan evaluation and project initiation preparation.

Qualifications

Minimum Qualifications

1. Bachelor's degree or above, graduated from relevant majors such as microelectronics / computer, with more than 2 years of APR work experience.

2. Have proficient scripting skills (e.g., TCL, Perl, Python, etc.).

3. Proficiently use mainstream backend tools and master basic backend concepts.

4. Have project experience with advanced processes, such as 7nm / 5nm / 3nm.

Preferred Qualifications

1. Good teamwork spirit and a serious and responsible work attitude.

2. Good communication skills, with fluent English reading and writing abilities.

Seniority level

• Mid‑Senior level

Employment type

Job function

Industries

#J-18808-Ljbffr