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Senior / Staff / Principal SoC RTL Design Engineer

2V SYSTEMS GLOBAL PTE LTDSingapore, Pedra Branca, Singapore

7 days ago

Job description

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Job Title : Senior / Staff SoC RTL Design Engineer ( Basic Monthly Salary SGD12K-SGD20K depending on Candidate Experience)

You will be a key member of our team working on a cutting-edge and complex System-on-Chip (SoC) product targeting high-performance computing with low power for data center servers. You will have the opportunity to contribute to all phases of the design lifecycle, from architecture definition to post-silicon validation support, with a significant focus on subsystem integration.

Lead and contribute to the micro-architecture definition and RTL implementation of complex digital blocks within the SoC.
Take a leading role in the RTL integration of major SoC subsystems, including but not limited to PCIe, CXL, and / or Coherent and Non-coherent Network-on-Chip (NoC) fabrics.
Translate high-level specifications and architectural requirements into detailed micro-architecture and RTL design for individual blocks and integrated subsystems.
Develop high-quality, synthesizable, and verifiable RTL code using Verilog or SystemVerilog for both individual modules and interconnect logic.
Perform rigorous design verification at both the block and subsystem levels through simulation, formal verification, and other advanced verification methodologies, with a focus on interface and integration aspects.
Collaborate closely with architects, IP providers, verification engineers, physical design engineers, and other stakeholders to ensure seamless subsystem integration.
Participate in and contribute to design reviews, specifically addressing integration challenges and ensuring interface compatibility.
Take ownership of assigned modules and integrated subsystems, ensuring they meet performance, power, area, and timing targets within the SoC context.
Develop and maintain comprehensive technical documentation, including design specifications, integration guidelines, verification plans, and test reports, with a strong emphasis on subsystem interfaces.
Mentor and provide technical guidance to junior engineers on the team, particularly in the area of RTL integration.
Participate in post-silicon bring-up and debug efforts, providing expert support for issues related to subsystem integration and interaction.
Stay abreast of the latest industry trends and advancements in SoC design, interconnect technologies, and integration methodologies.

Job requirements :

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Minimum of 10 years of hands-on experience inRTL design for complex SoCs.

Minimum of 3 to 5 years of direct experience in RTL integration of one or more major SoC subsystems with industrial IPs such as SNPS PCIe, CXL, and Arteris NoC.

Proven track record of successfully taking multiple complex digital designs and integrated subsystems from concept to tape-out.

Experience in designing or integrating for server chip that heavily utilize the targeted subsystems.

Strong expertise in Verilog or SystemVerilog RTL coding and simulation, with a focus on interface design and integration.

Proficiency in using industry-standard EDA tools for RTL simulation, synthesis, and static timing analysis (e.g., Cadence, Synopsys, Mentor Graphics), with experience in analyzing timing and connectivity across subsystem interfaces.

Experience with various verification methodologies, including UVM, constrained-random verification, and formal verification, with a focus on verifying inter-subsystem communication and functionality.

Solid understanding of digital design fundamentals, including timing, power, and area considerations, especially in the context of integrating diverse IP blocks.

Excellent problem-solving and debugging skills, particularly in identifying and resolving integration-relatedissues.

Strong communication and interpersonal skills, with the ability to collaborate effectively with diverse teams andIP providers during the integration process.

Ability to work independently and manage tasks effectively, including the coordination of integration efforts across different design teams.

Experience with scripting languages such as Python, Perl, or TCL for automation of integration tasks and analysis.

The reasons to join US :

Opportunity to work on cutting-edge SoC and chiplet technologies .

Flat and agile team structure that encourages innovation and technical ownership.

Competitive compensation and benefits.

A chance to influence next-generation silicon for AI, HPC, or next-gen data center platforms.

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Engineering and Information Technology

Industries

Technology, Information and Internet

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Design Engineer • Singapore, Pedra Branca, Singapore