Modeling Jobs in Singapore

Job Description[About the team]

MediaTek's Memory modelling team collaborates with the world-wide memory design teams to create and qualify front-end models for use in the ASIC design flow. Team members will also be expected to perform circuit design verification to ensure memory circuits robustness. The team is currently looking for fresh talent to join the dynamic team as a modeling engineer for the development of behavioral, FPGA, timing and DFT simulation models. The role will be required to create, debug and optimize SRAM models for ASIC design flow.

The candidate must be a team player, able to communicate clearly and concisely to deliver quality work on time.

What you do]

• Develop and integrate automation code into existing memory compilers to generate models meant for ASIC design flow.
• Develop automation flow and scripts with Perl or Python.
• Execute EDA tools from vendors such as Synopsys, Mentor to verify models’ correctness.
• Stay up to date with current modeling standards and development to improve models and flows for better memory IP performance.
• Work with memory design, compiler team and DFT team and tool vendors to resolve model issues and find solutions.Requirement[What you bring]
• Must have a Bachelor’s degree or higher in Electrical Engineering, Electronics Engineering, or related discipline with at least 3 years of semiconductor industry experience.
• Have at least 3 years experience using Linux systems.
• Good understanding of Verilog syntax and its various aspects, such as behavioral, RTL and synthesizable Verilog is a must.
• Good understanding of liberty timing syntax.
• Good understanding of upf and system Verilog.
• Knowledge and experience with EDA simulation tools such as VCS, NC is required.
• Experience with EDA tools will be helpful :

1.DFT : Logicvision, Tessent, Fastscan

2.Synthesis : Design compiler, Genus

3.Simulation tools : VCS, QuestaSim, NC

4.STA tools such as PrimeTime

Location : One North, Singapore