RTL Designer - D14 Geylang, Eunos, SG

Roles & Responsibilities

Job Responsibilities :

• Perform IC design development of SerDes IP products
• Perform Logic Synthesis, Static Timing Analysis
• Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation
• Work with Physical designer and RTL designer to achieve timing closure
• Work with test team in debugging production test issues
• Help debug & correct any functional issues found in taped-out devices
• Participate in design reviews, support ISO processes and documentation
• Work closely with customer’s Systems and Software engineers on FPGA verification

Requirements :

1. Digital and mixed-signal design

2. USB interface products

3. Graphics processor and driver products

4. Knowledge in connectivity technology such as USB, PCIe, MIPI, SPI, I2C

Tell employers what skills you have

Timing Closure

Analog

Architect

RTL Design

Cadence

DFT

ASIC

IC

Electrical Engineering

Silicon