(Sr.) ISP RTL Design Manager - D22 Jurong, Jurong Island, Tuas, SG

Roles & Responsibilities

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and / or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design leaders in other sites, and Digital System Design Team
• Leading, supervising and mentoring a team of RTL design engineers

Requirements

Tell employers what skills you have

Image Sensors

Image Processing

Signal and Image Processing

Interpersonal Skills

Digital Design

System Design

RTL Design

CMOS

System Verilog

Verilog

People Management Experience

Algorithms

Signal Processing