(Sr. / Staff) ISP RTL Design Engineer - D22 Jurong, Jurong Island, Tuas, SG

Roles & Responsibilities

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and / or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

Tell employers what skills you have

Image Sensors

Image Processing

Signal and Image Processing

RTL Coding

Digital Design

RTL Design

CMOS

SystemVerilog

C#

Debugging

Verilog

Algorithms

C++

Signal Processing