Roles & Responsibilities
Job Description
- Design and Develop ICs using leading EDA software; work on RTL to GDS, including synthesis, layout, floor planning, placement, clock tree insertion and routing.
- Responsible for GDS validation like DRC / LVS, timing closure sign-off, scan, validation etc.
- Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
- Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.
Job Requirements
Bachelor / Masters Degree in Electronics / Electrical / Computer Engineering with 1 year or more experienceGood experience and knowledge in design flow from Netlist to GDS, Synthesis, layout, Floor Planning, route , STA, CTS, RC Extraction and correlationStatic timing analysis, power and noise analysis and back-end verification across multiple projects.Proficient with backend design EDA tools, Synopsys ICC2 preferredSuccessfully track records of taping out complex SOCWorking knowledge of deep sub-micron routing issues as they relate to power and timing.Proficiency using Perl and TCLSelf-motivated team worker, good verbal and written communication skillsEthos Search Associates
EA Licence No : 13C6655
EA Reg No : R1109557 Rose
Tell employers what skills you have
Static Timing Analysis
Timing Closure
Analytical Skills
Floorplanning
EDA
UVM
IP
SoC
scripting language
Cadence
ASIC
RTL Synthesis
Debugging
IC
Physical Design
Verilog
Silicon