Roles & Responsibilities
Job Descriptions
- Develop and Review Test Plan based on IC design specification
- Develop constrained-Random verification environment for complex DUT
- Develop / Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP / ICs / SOCs and ensure product meet their performance
- Implement coverage matrix using cover point and assertion
- Create and debug tests for DUT
- Resolve bugs with remote designers
Requirements
Bachelor / Masters Degree in Electrical / Electronics / Computer Engineering with 1 year or more experienceHands-on experience in Silicon / IP verification using SystemVerilog / UVMStrong understanding of verification process from test plan to coverage completionStrong communication and Analytical skillsUnderstanding of HDL (Verilog, VHDL)Experience in using leading EDA software tools like Cadence / SynopsysEthos Search Associates Pte. Ltd.
EA Licence No : 13C6655
EA Reg No : R1109557 Rose
Tell employers what skills you have
design verification
Analytical Skills
Synopsys Tools
Digital IC Design
Test Cases
EDA
UVM
IP
SoC
SystemVerilog
Semiconductors
Semiconductor Device
Cadence
Functional Verification
ASIC
Electronic design automation (EDA)
Test Development
Debugging
IC
Verilog