Digital IC Verification Engineer (Senior)

Roles & Responsibilities

About the Role
We are seeking a Senior Digital IC Verification Engineer to lead verification development for high-speed DSP and digital subsystems used in optical communication systems. You will own verification activities from specification to sign-off, working closely with RTL, architecture, and system teams to ensure robust and high-quality ASIC/SoC designs.

Key Responsibilities:

· Define and drive verification strategies, plans, and coverage models for complex DSP and digital blocks.

· Develop and maintain scalable UVM/SystemVerilog verification environments for block and subsystem levels.

· Create constrained-random stimulus, assertions (SVA), and functional coverage to achieve verification closure.

· Lead debug activities, perform root cause analysis, and drive issue resolution with RTL designers.

· Own regression execution, coverage analysis, and sign-off criteria for assigned modules.

· Collaborate with system, DSP, and architecture teams to validate high-speed datapath behavior and corner cases.

· Contribute to methodology improvements, reusable verification IP, and automation flows.

· Mentor junior engineers and participate in code, testbench, and verification reviews.

Requirements:
· Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related fields.

· 5+ years of experience in digital IC verification (ASIC/SoC).

· Strong understanding of verification methodologies including UVM, constrained-random, and coverage-driven verification.

· Solid knowledge of digital design and micro-architecture concepts.

Tell employers what skills you have

Systems Flow
Establishing Plans
Root Cause Analysis
Digital IC Design
Coverage Analysis
Mentoring for Developers
Reviewing
improve methodologies
Verification Techniques
RTL Design
Lead Sales Activities
Software Verification Procedures
Interfacing Systems
Functional Verification
regression scripts
DSP Algorithms