Logic Verification Engineer

Roles & Responsibilities

Responsibilities :

• Perform chip verification for new product development.
• Participate in IP- and system-level simulation verification.
• Develop and maintain UVM-based verification environments according to architectural documentation.
• Define and achieve functional coverage targets; improve code and functional coverage based on the verification plan.
• Execute verification across gate-level and post-simulation stages; debug issues, resolve cases, and ensure verification tasks are completed at each project milestone.
• Support validation requirements and contribute to successful tape-out.

Qualifications :

Tell employers what skills you have

Perl

Architectural

Documentation Skills

Scripting

EDA

UVM

SoC

Python

Ethernet

Flash

Functional Verification

ASIC

Product Development

Verilog

Electrical Engineering

VLSI