Design Verification Engineer (SoC / ASIC / RTL)

Roles & Responsibilities

Responsibilities :

• Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
• Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
• Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
• Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
• Collaborate with design engineers to troubleshoot and resolve simulation issues.
• Provide support to test engineers during post-silicon validation.
• Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.​

Requirements :

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HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact win@hkmsvs.com for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and / or last employment

2) Last drawn and / or current salary

3) Expected salary

4) Date of availability and / or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Tell employers what skills you have

Perl

TCL

Architects

Documentation Skills

Scripting

MIPI

Test Cases

UVM

SoC

Python

SystemVerilog

Functional Verification

ASIC

Verilog

Electrical Engineering

VLSI